27

Sensitive photonic crystal phase logic gates

Year:
2009
Language:
english
File:
PDF, 426 KB
english, 2009
31

CPSiCGF: A code generation framework for CPS integration modeling

Year:
2015
Language:
english
File:
PDF, 3.82 MB
english, 2015
33

A clock synchronization method for EtherCAT master

Year:
2016
Language:
english
File:
PDF, 2.04 MB
english, 2016
41

Position 22 of the V3 loop is associated with HIV infectivity

Year:
2017
Language:
english
File:
PDF, 1.09 MB
english, 2017